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hy5du281622et 128m(8mx16) gddr sdram hy5du281622et this document is a general product descript ion and is subject to change without notice. hynix electronics does not assume any r espon- sibility for use of circuits described. no patent licenses are implied. rev. 0.5 / jan. 2005 1
rev. 0.5 / jan. 2005 2 hy5du281622et revision history revision no. history draft date remark 0.1 defined target spec. july 2003 0.2 1) insert overshoot/und ershoot specification 2) insert tdss/tdsh parameter oct. 2003 0.3 tpdex value change mar. 2004 0.4 trc_apcg changed to 12 clock from 11 clock at 166mhz speed bin oct. 2004 0.5 166mhz speed bin delete, ac parameter change (trc_apcg at 200mhz) jan. 2005
rev. 0.5 / jan. 2005 3 hy5du281622et description the hynix hy5du281622et is a 134,217,728-bit cmos double data rate(ddr) synchronous dram, ideally suited for the point-to-point applications which re quire high densities and high bandwidth. the hynix 8mx16 ddr sdrams offer fully synchronous operatio ns referenced to both rising and falling edges of the clock. while all addresses and control inpu ts are latched on the rising edges of th e ck (falling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ? 2.8v +/- 0.1v v dd and v ddq power supply supports 400/375/350/333/300mhz ?2.5v +/- 5% v dd and v ddq power supply supports 275/250/200/166mhz ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 400 mil x 875 mil 66 pin tsop ii, with 0.65mm pin pitch ? fully differential clock in puts (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (udqs,ldqs) ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? data(dq) and write masks(dm) latched on the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? write mask byte cont rols by dm (udm,ldm) ? programmable /cas latency 5, 4 and 3 are sup- ported ? programmable burst length 2, 4 and 8 with both sequential and interleave mode ? internal 4 bank operation with single pulsed /ras ? tras lock-out function are supported ? auto refresh and self refresh are supported ? 4096 refresh cycles / 32ms ? full strength, half strength and weak impedance driver options controlled by emrs ordering information part no. power supply clock frequency max data rate interface package hy5du281622et-25 vdd/vddq=2.8v 400mhz 800mbps/pin sstl_2 400 x 875mil 2 66 pin tsop ii hy5du281622et-26 375mhz 750mbps/pin hy5du281622et-28 350mhz 700mbps/pin HY5DU281622ET-30 333mhz 666mbps/pin hy5du281622et-33 300mhz 600mbps/pin hy5du281622et-36 vdd/vddq=2.5v 275mhz 550mbps/pin hy5du281622et-4 250mhz 500mbps/pin hy5du281622et-5 200mhz 400mbps/pin
rev. 0.5 / jan. 2005 4 hy5du281622et pin configuration (top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss 400mil x 875mil 66pin tsop -ii 0.65mm pin pitch row and column address table items 8mx16 organization 2m x 16 x 4banks row address a0 - a11 column address a0-a8 bank address ba0, ba1 auto precharge flag a10 refresh 4k
rev. 0.5 / jan. 2005 5 hy5du281622et pin description pin type description ck, /ck input clock: ck and /ck are differen tial clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry and exit. cke is asynchronous for output disable. cke must be main- tained high throughout read and write acce sses. input buffers, excluding ck, /ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cke is an sstl _2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. udm, ldm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high al ong with that input data during a write access. dm is sampled on both edges of dqs. although dm pins ar e input only, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0-q7; udm corresponds to the data on dq8-q15 u d q s , l d q s i / o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture wr ite data. ldqs corresponds to the data on dq0-q7; udqs corresponds to the data on dq8-q15 dq0 ~ dq15 i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 0.5 / jan. 2005 6 hy5du281622et functional block diagram 4banks x 2mbit x 16 i/o double data rate synchronous dram dq[0:15] bank control write data register 2-bit prefetch unit clk cke ldm /we /ras /cas /cs /clk mode register row decoder sense amp 2mx16/bank0 2mx16/bank3 2mx16/bank2 2mx16/bank1 2-bit prefetch unit output buffer input buffer data strobe transmitter dll block a0~a11 column address counter column decoder data strobe receiver command decoder address buffer 32 16 16 clk /clk 32 ds ldqs, udqs clk_dll ldqs udqs mode register udm ba0, ba1
rev. 0.5 / jan. 2005 7 hy5du281622et simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register seth x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. udm, ldm states are don?t care. refer to below write mask truth table.(note 6) 2. op code(operand code) consists of a0 ~a11 and ba0~ba1 used for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with auto-precharge command is detected by memo ry component in ck(n), then there will be no command presented to activate bank until ck(n+bl/2+trp). 4. if a write with auto-precharge command is detected by memory component in ck(n ), then there will be no command presented to activate bank until ck(n+bl/2+1+tdpl+trp). last data-in to prechage delay(tdpl) which is also called write recovery time(twr) is needed to guarantee that the last data have been completely written. 5. if a10/ap is high when precharge co mmand being issued, ba0/ba1 are ignored and all banks are selected to be precharged. 6. in here, don?t care means logical value only, it doesn?t mean ?don?t care for dc level of each signals?. dc level should be out of v ihmin ~ v ilmax ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
rev. 0.5 / jan. 2005 8 hy5du281622et write mask truth table function cken-1 cken /cs, /ras, /cas, /we dm addr a8/ ap ba note data write h x x l x 1,2,3 data-in mask h x x h x 1,2,3 note : 1. write mask command masks burst write data with reference to udqs/ldqs and it is not related with read data. 2. ldm corresponds to the data on dq0-q7 and udm corresponds to the data on dq8-q15 3. in here, don?t care means logical value only, it doesn?t mean ?don?t care for dc level of each signals?. dc level should be out of v ihmin ~ v ilmax
rev. 0.5 / jan. 2005 9 hy5du281622et operation command truth table - i current state /cs /ras /cas /we address command action idle hxxx x dsel nop or power down 3 lhhh x nop nop or power down 3 lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation llhl ba, ap pre/pall nop lllh x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active hxxx x dsel nop lhhh x nop nop lhhl x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 llhhba, ra act illegal 4 llhl ba, ap pre/pall precharge 7 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 0.5 / jan. 2005 10 hy5du281622et operation command truth table - ii current state /cs /ras /cas /we address command action write llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.5 / jan. 2005 11 hy5du281622et operation command truth table - iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,9,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
rev. 0.5 / jan. 2005 12 hy5du281622et operation command truth table - iv note : 1. h - logic high level, l - logic low level, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge ad dress, ca - column address, ra - row address, nop - no operation.(see note 12) 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be lega l in the bank indicated by bank address(ba) depending on the stat e of that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. 12. in here, don?t care means logical value only, it doesn?t mean ?don?t care for dc level of ea ch signals?. dc level should b e out of v ihmin ~ v ilmax current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.5 / jan. 2005 13 hy5du281622et cke function truth table note : when cke=l, all dq and udqs/ldqs should be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all commands can be stored after 2 clocks from low to high transition of cke. 3. illegal, if ck is suspended or stopped during the power down mode. 4. self refresh can be asserted only from the all banks idle state. 5. disabling ck may cause malfunction of any banks which are in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h xxxxxx invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex lhlhhlx illegal lhlhlxx illegal l hllxxx illegal l lxxxxx nop, continue self refresh power down 2 h xxxxxx invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle lhlhhlx illegal lhlhlxx illegal l hllxxx illegal l l x x x x x nop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table hllllhx enter self refresh h l h x x x x exit power down h l l h h h x exit power down hllhhlx illegal hllhlxx illegal hlllhxx illegal hlllllx illegal l lxxxxx nop any state other than above h h x x x x x see operation command truth table h lxxxxx illegal 5 l hxxxxx invalid l lxxxxx invalid
rev. 0.5 / jan. 2005 14 hy5du281622et simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
rev. 0.5 / jan. 2005 15 hy5du281622et power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational pr ocedures other than those specified may result in undefined operation. except for ck e, inputs are not re cognized as valid until after vref is applied. cke is an sstl_2 input, but will detect an lv cmos low level after vdd is applied. maintaining an lvcmos low level on cke during power-up is required to guarant ee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all po wer supply and reference volt- ages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable com- mand. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to enable the dll, then a mode register set command should be issued for the mode re gister, to reset the dll, and to program the operating parameters. after the dll reset, txsrd(dll locking time) sh ould be satisfied for read command. after the mode reg- ister set command, a precharge all command should be a pplied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated lo w (i.e. to program operating parameters without resetting the dll) must be performed. following these cycl es, the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the following po wer up sequencing and attemp t to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) no power sequencing is specified during power up or power down given the following cirteria : ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.4025v (reflecting vddq(max)/ 2 + 50mv vref variation + 40mv vtt variation). ? vref tracks vddq/2. ? if the above criteria cannot be met by the system design, then the following sequ encing and voltage relation- ship must be adhered to during power up : 2. start clock and maintain stab le clock for a minimum of 200 sec. 3. after stable power and clock, apply nop or deselect conditions and take cke high. 4. following the nop command, a precha rge all command should be applied 5. issue extended mode register set (emrs) to enable dll. 6. issue mode register set (mrs) to reset dll and set devi ce to idle state with bit a8=high. (an additional 200 cycles(txsrd) of clock are required for locking dll) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto refresh commands. voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
rev. 0.5 / jan. 2005 16 hy5du281622et 9. issue a mode register set command to initia lize the mode register with bit a8 = low. power-up sequence code code code code code code code code code code code code code code code nop pre mrs emrs pre nop mrs aref act rd vdd vddq vtt vref /clk clk cke cmd dm addr a10 ba0, ba1 dqs dq's lvcmos low level tis tih tvtd t=200usec trp tmrd trp trfc tmrd txsrd* read non-read command power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) * 200 cycle(txsrd) of ck are required (for dll locking) before read command tmrd
rev. 0.5 / jan. 2005 17 hy5du281622et mode register set (mrs) the mode register is used to store the various operating mo des such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogram via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. two cycles are required to write the data in mode register. during the the mrs cycle, an y command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a7 te s t mo de 0normal 1 vendor test mode a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu* dr tm cas latency bt burst length * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage. and, if mrs/emrs are programmed with ?reserved? code, it could be the cause of mal-function. a6 a5 a4 cas latency 000 reserved 001 reserved 010 reserved 011 3 100 4 101 5 110 reserved 111 reserved
rev. 0.5 / jan. 2005 18 hy5du281622et burst definition burst length & type read and write accesses to the ddr sdram are burst orient ed, with the burst length be ing programmable. the burst length determines the maximum number of column locations that can be acce ssed for a given read or write com- mand. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eigh t (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; th is is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column addres s, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
rev. 0.5 / jan. 2005 19 hy5du281622et cas latency the read latency or cas latency is the delay in clock cy cles between the registration of a read command and the availability of the first burst of output data . the latency can be programmed 3 or 4 clocks. if a read command is registered at clock edge n, and the la tency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for th e purpose of debug or evaluation. the dll is automatically disabled when entering self refresh oper ation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal clock to lock to the externally applied clock before an any command can be issued. output driver impedance control this device supports both half strength driver and matched impedance driver, inte nded for lighter load and/or point-to- point environments. half strength driver is to define about 50% of full drive st rength which is specified to be sstl_2, class ii, and matched impedance driver, about 30% of full drive strength.
rev. 0.5 / jan. 2005 20 hy5du281622et extended mode register set (emrs) the extended mode register controls fu nctions beyond those controlled by the mode register; these additional func- tions include dll enable/disable, output dr iver strength selection(optional). thes e functions are contro lled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before in itiating any subsequent operation. viol ating either of these requirements will result in unspecified operation. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* ds rfu* ds dll a0 dll enable 0enable 1diable ba0 mrs type 0mrs 1emrs a6 a1 output driver impedance control 00 full 0 1 half (60%) 10 reserved 11 weak (33%) * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage.
rev. 0.5 / jan. 2005 21 hy5du281622et absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. vref is expected to be equal to 0.5*vddq of th e transmitting device, and to track variations in the dc level of th e same. peak to peak noise on vref may not exceed 2% of the dc value. 3. vtt is expected to be set equal to vref, and vtt of the transmitting device must track vref of the receiving device. 4. supports 275/ 250/ 200/166mhz 5. supports 400/375/350/333/300mhz dc characteristics i (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pins are not tested under v in =0v. 2. d out is disabled, v out =0 to 2.625v, it means, output logic high voltage and low voltage is depend on output channel conditions. parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 2w soldering temperature ? time t solder 260 ? 10 o c ? sec parameter symbol min typ max unit note power supply voltage v dd 2.375 2.5 2.625 v 1,4 v ddq 2.375 2.5 2.625 v 1,4 v dd 2.7 2.8 2.9 v 1,5 v ddq 2.7 2.8 2.9 v 1,5 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v 3 reference voltage v ref 0.49*v ddq 0.5*v ddq 0.51*v ddq v2 parameter symbol min max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma,2 output low voltage v ol -v tt - 0.76 v i ol = +15.2ma,2
rev. 0.5 / jan. 2005 22 hy5du281622et dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. i dd1, idd4 and i dd5 depend on output loading and cycle rates. spec ified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. parameter symbol test condition speed unit note 25 26 28 30 33 operating current i dd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 230 220 210 200 190 ma 1 operating current i dd1 b u r s t l e n g t h = 4 , o n e b a n k a c t i v e t rc t rc (min), i ol =0ma 230 220 210 200 190 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck =min 40 40 40 40 40 ma precharge standby current in non power down mode i dd2n cke v ih (min), /cs v ih (min), t ck = min, input signals are changed one time during 2clks 150 140 130 120 110 ma active standby cur- rent in power down mode i dd3p cke v il (max), t ck =min 40 40 40 40 40 ma active standby cur- rent in non power down mode i dd3n cke v ih (min), /cs v ih (min), t ck =min, input signals are changed one time during 2clks 190 180 170 160 150 ma burst mode operating current i dd4 t ck t ck (min), i ol = 0 m a all banks active 380 360 340 320 300 ma 1 auto refresh current i dd5 t rc t rfc ( m i n ) , all banks active 380 360 340 320 300 ma 1,2 self refresh current i dd6 cke 0.2v 44444ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 530 510 490 470 450 ma
rev. 0.5 / jan. 2005 23 hy5du281622et dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. i dd1, idd4 and i dd5 depend on output loading and cycle rates. spec ified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. parameter symbol test condition speed unit note 36 4 5 operating current i dd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 180 170 160 ma 1 operating current i dd1 b u r s t l e n g t h = 2 , o n e b a n k a c t i v e t rc t rc (min), i ol =0ma 180 170 160 ma 1 precharge standby cur- rent in power down mode i dd2p cke v il (max), t ck =min 40 40 40 ma precharge standby cur- rent in non power down mode i dd2n cke v ih (min), /cs v ih (min), t ck = min, input signals are changed one time during 2clks 100 90 80 ma active standby current in power down mode i dd3p cke v il (max), t ck =min 40 40 40 ma active standby current in non power down mode i dd3n cke v ih (min), /cs v ih (min), t ck =min, input signals are changed one time during 2clks 140 130 120 ma burst mode operating cur- rent i dd4 t ck t ck (min), i ol = 0 m a all banks active 280 260 240 ma 1 auto refresh current i dd5 t rc t rfc (min ), all banks active 280 260 240 ma 1,2 self refresh current i dd6 cke 0.2v 4 4 4 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 430 410 390 ma
rev. 0.5 / jan. 2005 24 hy5du281622et ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.45 v input low (logic 0) voltag e, dq, dqs and dm signals v il(ac) v ref - 0.45 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.45 v ac input low level voltage (v il , max) v ref - 0.45 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf
rev. 0.5 / jan. 2005 25 hy5du281622et ac overshoot/undershoot specifications for address and command pins ac overshoot/undershoot specifications for data, strobe and mask pins parameter 200mhz specifications maximum peak amplitude allowwed for overshoot 1.5 v maximum peak amplitude allowwed for undershoot 1.5 v the area between the overshoot signal and vdd must be less than or equal to(see below fig) 4.5 v-ns the area between the overshoot signal and gnd must be less than or equal to(see below fig) 4.5 v-ns parameter 200mhz specifications maximum peak amplitude allowwed for overshoot 1.2 v maximum peak amplitude allowwed for undershoot 1.2 v the area between the overshoot signal and vdd must be less than or equal to(see below fig) 2.4 v-ns the area between the overshoot signal and gnd must be less than or equal to(see below fig) 2.4 v-ns v dd 0123456 0 +1 +2 +3 +4 +5 -1 -2 -3 volts (v) time(ns) ground max. area=4.5v-ns max. amplitude=1.5v v dd 0123456 0 +1 +2 +3 +4 +5 -1 -2 -3 volts (v) time(ns) ground max. area=2.4v-ns max. amplitude=1.2v
rev. 0.5 / jan. 2005 26 hy5du281622et ac characteristics - i (ac operating conditions unless otherwise noted) parameter symbol 25 26 28 unit note min max min max min max row cycle time(manual precharge) t rc 22 - 21 - 20 - ck row cycle time(auto precharge) trc_apcg 24 - 23 - 22 - auto refresh row cycle time t rfc 26 - 25 - 24 - ck row active time t ras 16 100k 15 100k 14 100k ck row address to column address delay for read t rcdrd 6- 6 -6- ck row address to column address delay for write t rcdwr 4- 4 -4- ck row active to row active delay t rrd 4- 4 -4- ck column address to column address delay t ccd 2- 2 -2- ck row precharge time t rp 6- 6 -6- ck write recovery time t wr 4- 4 -4- ck last data-in to read command t drl 2- 2 -2- ck auto precharge write recovery + precharge time t dal 10 - 10 - 10 - ck system clock cycle time cl=5 t ck 2.5 6 2.6 6 - - ns cl=4 -- - -2.86 clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.55 0.55 -0.6 0.6 -0.6 0.6 ns dqs-out edge to clock edge skew t dqsck -0.55 0.55 -0.6 0.6 -0.6 0.6 ns dqs-out edge to data-out edge skew t dqsq - 0.35 - 0.35 - 0.35 ns data-out hold time from dqs t qh thpmin -tqhs - thpmin -tqhs - thpmin -tqhs - ns 1,6 clock half period t hp tch/l min - tch/l min - tch/l min - ns 1,5 data hold skew factor t qhs - 0.35 - 0.35 - 0.35 ns 6 input setup time t is 0.75 - 0.75 - 0.75 - ns 2 input hold time t ih 0.75 - 0.75 - 0.75 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.85 1.15 0.85 1.15 0.85 1.15 ck data-in setup time to dqs-in (dq & dm) t ds 0.35 - 0.35 - 0.35 - ns 3 data-in hold time to dqs-in (dq & dm) t dh 0.35 - 0.35 - 0.35 - ns 3
rev. 0.5 / jan. 2005 27 hy5du281622et n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling e dges of data strobes(udqs,ldqs) : dq, ldm,udm. 4. minimum of 200 cycles of stable input clocks after self refres h exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 6. thp = minimum half clock period for any given cycl e and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width dist ortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prev ent double clocking of data and preserve setup and hold times. signal transitions throug h the dc region must be monotonic. parameter symbol 25 26 28 unit note min max min max min max dqs falling edge to ck setup time tdss 3.0 - 3.0 - 3.0 - ck dqs falling edge hold time from ck tdsh 3.0 - 3.0 - 3.0 - ck write dqs preamble setup time t wpres 0- 0 -0- ns write dqs preamble hold time t wpreh 0.35 - 0.35 - 0.35 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 10 - 10 - 10 - ns exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 4 power down exit time t pdex 2tck + tis - 2tck + tis - 2tck + tis - ck average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 us
rev. 0.5 / jan. 2005 28 hy5du281622et ac characteristics - i (ac operating conditions unless otherwise noted) parameter symbol 30 33 36 unit note min max min max min max row cycle time(manual precharge) t rc 19 - 18 - 16 - ck row cycle time(auto precharge) trc_apcg 21 - 20 - 18 - auto refresh row cycle time t rfc 23 - 22 - 20 - ck row active time t ras 13 100k 12 100k 11 100k ck row address to column address delay for read t rcdrd 6- 6 -5- ck row address to column address delay for write t rcdwr 4- 4 -3- ck row active to row active delay t rrd 4- 4 -3- ck column address to column address delay t ccd 2- 1 -1- ck row precharge time t rp 6- 6 -5- ck write recovery time t wr 4- 4 -3- ck last data-in to read command t drl 2- 2 -2- ck auto precharge write recovery + precharge time t dal 10 - 10 - 8 - ck system clock cycle time cl=4 t ck 363.363.610 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.6 0.6 -0.6 0.6 -0.6 0.6 ns dqs-out edge to clock edge skew t dqsck -0.6 0.6 -0.6 0.6 -0.6 0.6 ns dqs-out edge to data-out edge skew t dqsq - 0.35 - 0.35 - 0.35 ns data-out hold time from dqs t qh thpmin -tqhs - thpmin -tqhs - thpmin -tqhs - ns 1,6 clock half period t hp tch/l min - tch/l min - tch/l min - ns 1,5 data hold skew factor t qhs - 0.35 - 0.35 - 0.4 ns 6 input setup time t is 0.75 - 0.75 - 0.75 - ns 2 input hold time t ih 0.75 - 0.75 - 0.75 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.85 1.15 0.85 1.15 0.85 1.15 ck data-in setup time to dqs-in (dq & dm) t ds 0.35 - 0.35 - 0.4 - ns 3 data-in hold time to dqs-in (dq & dm) t dh 0.35 - 0.35 - 0.4 - ns 3
rev. 0.5 / jan. 2005 29 hy5du281622et n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling e dges of data strobes(udqs,ldqs) : dq, ldm,udm. 4. minimum of 200 cycles of stable input clocks after self refres h exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 6. thp = minimum half clock period for any given cycl e and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width dist ortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prev ent double clocking of data and preserve setup and hold times. signal transitions throug h the dc region must be monotonic. dqs falling edge to ck setup time tdss 0.3 - 0.3 - 0.3 - ck dqs falling edge hold time from ck tdsh 0.3 - 0.3 - 0.3 - ck read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0- 0 -0- ns write dqs preamble hold time t wpreh 0.35 - 0.35 - 0.35 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 10 - 10 - 10 - ns exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 4 power down exit time t pdex 2tck + tis - 2tck + tis - 2tck + tis - ck average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 us parameter symbol 30 33 36 unit note min max min max min max
rev. 0.5 / jan. 2005 30 hy5du281622et ac characteristics - i (continued) parameter symbol 4 5 unit note min max min max row cycle time(manual precharge) t rc 15 - 12 - ck row cycle time(auto precharge) trc_apcg 17 - 13 - auto refresh row cycle time t rfc 18 - 14 - ck row active time t ras 10 100k 8 100k ck row address to column address delay for read t rcdrd 5-4- ck row address to column address delay for write t rcdwr 3-2- ck row active to row active delay t rrd 3-2- ck column address to column address delay t ccd 1-1- ck row precharge time t rp 5-4- ck write recovery time t wr 3-3- ck last data-in to read command t drl 2-2- ck auto precharge write recovery + precharge time t dal 8-7- ck system clock cycle time cl=4 t ck 410- - ns cl=3 --510 clock high level width t ch 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.6 0.6 -0.65 0.65 ns dqs-out edge to clock edge skew t dqsck -0.6 0.6 -0.55 0.55 ns dqs-out edge to data-out edge skew t dqsq -0.4-0.4 ns data-out hold time from dqs t qh thpmin -tqhs - thpmin -tqhs - ns 1,6 clock half period t hp tch/l min - tch/l min - ns 1,5 data hold skew factor t qhs - 0.4 - 0.45 ns 6 input setup time t is 0.75 - 0.6 - ns 2 input hold time t ih 0.75 - 0.6 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.85 1.15 0.72 1.28 ck
rev. 0.5 / jan. 2005 31 hy5du281622et n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling e dges of data strobes(udqs,ldqs) : dq, udm,ldm. 4. minimum of 200 cycles of stable input clocks after self refres h exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 6. thp = minimum half clock period for any given cycl e and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width dist ortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prev ent double clocking of data and preserve setup and hold times. signal transitions throug h the dc region must be monotonic. data-in setup time to dqs-in (dq & dm) t ds 0.4-0.4- ns 3 data-in hold time to dqs-in (dq & dm) t dh 0.4-0.4- ns 3 dqs falling edge to ck setup time tdss0.3-0.3- ck dqs falling edge hold time from ck tdsh 0.3-0.3- ck read dqs preamble time t rpre 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0- ns write dqs preamble hold time t wpreh 0.35 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 10 - 10 - ns exit self refresh to any execute command t xsc 200 - 200 - ck 4 power down exit time t pdex 2tck + tis - 2tck + tis - ck average periodic refresh interval t refi -7.8-7.8 us parameter symbol 4 5 unit note min max min max
rev. 0.5 / jan. 2005 32 hy5du281622et ac characteristics - ii frequency cl trc trc_apcg trfc tras trcdrd trcdwr trp tdal unit 400mhz (2.5ns) 5 22 24 26 16 6 4 6 10 tck 375mhz (2.6ns) 5 21 23 25 15 6 4 6 10 tck 350mhz (2.8ns) 4 20 22 24 14 6 4 6 10 tck 333mhz (3.0ns) 4 19 21 23 13 6 4 6 10 tck 300mhz (3.3ns) 4 18 20 22 12 6 4 6 10 tck 275mhz (3.6ns) 4 16 18 20 11 5 3 5 8 tck 250mhz (4.0ns) 4 15 17 18 10 5 3 5 8 tck 200mhz (5.0ns) 3 12 13 14 8 4 2 4 7 tck
rev. 0.5 / jan. 2005 33 hy5du281622et capacitance (t a =25 o c, f=1mhz ) note : 1. v dd = min. to max., v ddq = 2.375v to 2.625v, v o dc = v ddq /2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c ck 23pf input capacitance all other input-only pins c in 23pf input / output capacitance dq, dqs, dm c io 45pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
rev. 0.5 / jan. 2005 34 hy5du281622et package information 400mil 66pin thin sm all outline package 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch)

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